Advances in the field of semiconductor integrated circuits have brought about higher levels of integration. Accordingly, semiconductor manufacturing process advancements are driving the corresponding geometric dimensions of semiconductor devices to decreasingly smaller values. 10 micrometer (μm) gate lengths, for example, were common in the 1970's, but continuously advancing semiconductor manufacturing processes have reduced gate lengths to well below 100 nanometers (nm). One key driver for these semiconductor manufacturing process advancements is the ability to quickly characterize failure mechanisms for each new manufacturing process technology so that production yields may be increased in a timely manner.
To further advance integration, multiple layers are incorporated into the integrated circuits so as to accommodate additional features and functionality within the integrated circuits. Some of the layers of the integrated circuits may be implemented as metal layers that provide the means to implement voltage and voltage reference planes within the integrated circuit. Other layers within the integrated circuit may be used to implement semiconductor features/devices and their corresponding interconnect. One or more conductive layers and/or signal traces may also be interconnected using vertical conductive tunnels, i.e., vias, that provide a conduction path between the one or more layers and associated interconnect.
Interconnect vias require a minimum diameter, so as to facilitate proper metallization of the via during the metallization stage of the manufacturing process. If the via diameter is too small, for example, incomplete metallization of the via may occur, which may cause the via to exhibit an abnormally high impedance characteristic as a consequence of the incomplete metallization of the via. As such, the via may be characterized as a defective structure contained within the integrated circuit.
Conventional techniques that may be used to characterize defective structures within integrated circuits are invasive, since in order to obtain exposure of the metal layers, signal traces, and/or vias, top layers of the integrated circuit must be sequentially removed until adequate exposure of the test area is obtained. Utilization of such a technique, however, results in an integrated circuit that is no longer useful for its intended purpose because the integrated circuit is generally non-functional after the measurements are complete due to the planarized destruction of the integrated circuit that is required to obtain access to the structures of interest.
In addition, such a planarized exposure technique does not allow for the characterization of vertical structures within the integrated circuit, since only a single layer of the integrated circuit may be exposed at any given time. Other similarly invasive techniques utilize a focused ion beam (FIB) to extract a portion of the semiconductor die to be analyzed. Once severed, the semiconductor die portion may then be analyzed with a scanning transmission electron microscope (STEM) or a transmission electron microscope (TEM) in an attempt to discover the failure mode.
Conventional integrated circuits may also be implemented within wafers that employ specialized test structures. Such specialized test structures may be mechanically probed using pre-defined test pads to determine the condition of the test structure. Conventional de-processing techniques may then be employed once the test structures are found to be defective. However, such de-processing techniques generally result in a wafer that must be discarded.
Thus, while conventional techniques are available to ascertain the failure modes and abnormalities within integrated circuits, invasive procedures must be invoked to determine the failure mode, which generally renders the integrated circuit unusable thereafter. Furthermore, such invasive procedures are relatively inadequate to properly characterize vertical structures that may be contained within the integrated circuit.
Efforts continue, therefore, to provide a technique whereby features within an integrated circuit may be characterized while substantially avoiding destruction of the integrated circuit once characterization is complete. In addition, improved techniques to more accurately characterize vertical structures within the integrated circuits are needed.